The present invention is directed to random access memory circuits, and more specifically to static random access memory circuits. In a particular preferred embodiment, the present invention provides an improved variable clamp memory circuit of the type disclosed in commonly assigned, copending application Ser. No. 872,292 filed June 9, 1986, now U.S. Pat. No. 4,745,580.
A conventional static random access memory is comprised of an array of memory cells, each of which includes a cross-coupled pair of transistors that form a bistable latch circuit which stores one bit of binary data. In accordance with the particular bit of data that is stored in a cell, one of the cross-coupled transistors is on, i.e. in a conductive state, and the other transistor is off. The voltage present at the collector of the transistor which is off is at a high level relative to that at the collector of the transistor which is on. The difference between the voltages at the two collectors is often referred to as the cell voltage swing, and its polarity is detected to determine the bit of data stored in the cell. Typically, this detection is carried out by means of a pair of bit lines that are respectively connected to the emitters of the transistors in the cross-coupled pair.
The writing of a bit of data into a cell is accomplished by driving the appropriate one of the two transistors into its conductive state. Basically, this procedure involves pulling the voltage on the bit line connected to the appropriate transistor to a level which is sufficiently low to cause that transistor to conduct. If desired, the voltage on the other bit line can be raised at the same time to reduce the base-emitter voltage of the other transistor in the cell, thereby rendering it less conductive.
In an effort to decrease the time required to write a bit of data into a cell, and hence increase the operating speed of the memory, it is desirable to avoid saturation and minority carrier storage in the cross-coupled transistors. To this end, it is a general design objective to make the voltage swing of the cell as small as possible. In addition to avoiding saturation, a small cell swing reduces the voltage excursion which must take place each time the stored bit is changed from one binary value to its complement.
However, the objective of having a small voltage swing for a cell poses significant limitations in the overall design of the memory circuit, particularly with regard to noise immunity. Specifically, the determination of the relative polarity of the bit lines, i.e. the reading of data, is carried out with reference to a read threshold voltage. This threshold voltage must be at a value between the high and low voltage levels of the cell's collector nodes, and is preferably near the midpoint of these two levels. It will be appreciated that, as the cell swing is made smaller, the design specifications for the read voltage become more stringent. In particular, they require a precise determination of the high and low voltages, and their range of variation must also be known. Once the proper read threshold voltage is determined, it must be maintained within strict limits. If noise in the read threshold voltage or in the word line voltage should be sufficient to bring the read level above the cell high voltage or below its low voltage, data could be lost or read incorrectly.